Today I write a simple laboratory about a Mealy machine: a circuit that counts forward and backward in a two-bit binary sequence, respectively from 00 to 01 to 10 to 11 and from 11 to 10 to 01 to 00. The state diagram of the counter should look like in the next figure, and if you want to simulate it with JFLAP you can download it through 20151029_Two-bit_binary_up_and_down_counter.jff (to download it click with right button of your mouse on the link and select Save destination...).

JFLAP simulationOpen this file in JFLAP, click on Input>Fast Run and click the button Click to Open Input File to load a text file that you created earlier, that report a sequence 11110000, so the machine do a complete up count and then a conplete down count. For example you can use this file: input.txt. Alternatively you can use JFLAP 8 beta to simulate this finite automata, clicking on Input>Multiple Run, so you can try the inputs as shown in figure. So we can see that the automa works according to our requirements.
Now we can design the circuit of the counter and simulate it in NI Multisim. The following figures show the table next state x0(t+1) and x1(t+1) with its map of Karnaugh and table output u0(t) and u1(t), it is composed of two signals. They depend from the inputs i (t), x0(t) and x1(t). The output concide with the next state, so it is derived from the same combinational circuit. Finally, two flip flop DFF store the next state.

Karnaugh map

Now I open Multisim 13 (but what I write works also for oldest versions 11 and 12) and I write to you how simulate the counter. Access to the Multisim PLD environment selecting File>New>PLD Design and following the wizard in three steps. In the box that opens to Step 1 of 3 choose the option Create empty PLD, in order to design a PLD Multisim simulation environment. At Step 2 of 3 denote the PLD design name of our project, and at Step 3 of 3 is required to switch on the power pin of the device (the information is needed for a correct simulation: put 3.3 V for all connectors, input, output, and bidirectional).
Once realized the device and before saving it, is useful to check if there are errors on the schematic or warnings to be considered. Start the test through Tools>PLD Topology Chek, and take action to fix errors.
So you can save the PLD just created and then you can use it in any of our schematic within Multisim 13 or later, or export it to a VHDL file for use in other software applications that synthesize it aboard a CPLD or FPGA real.
Schematic is reported in the figure below and disponible to download for Multisim 13 version and latest: 20151030_ContatoreModulo4.ms13
Counter PLD

Then open a new Blank design of Multisim 13 that you need to test the behavior of the counter just realized. To import the schematic inside the PLD, you should click Place>Hierarchical Block from file and open the file of the counter. This will appear as a single device accessible through its pin I/O. Connect at its inputs a square wave generator 3.3V 100Hz and a switch in pull-up configuration; bring the outputs on two LEDs protected by resistors placed in series.

You can download simulation file here: 20151030_Simulazione_ContatoreModulo4_Avanti-Indietro.ms13